1. Field of the Invention
Generally, the present disclosure relates to integrated circuits and methods for the formation thereof, in particular to integrated circuits wherein field effect transistors including gate structures having a gate insulation layer wherein a high-k material is provided are formed.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements, in particular field effect transistors. In a field effect transistor, a gate structure including a gate electrode and a gate insulation layer that provides electrical insulation between the gate electrode and the channel region may be provided. Adjacent the channel region, a source region and a drain region that are doped differently than the channel region are provided. Depending on an electric voltage applied to the gate electrode, the field effect transistor can be switched between an on-state and an off-state, wherein an electrical conductivity of the channel region in the on-state is greater than an electrical conductivity of the channel region in the off-state.
Integrated circuits including field effect transistors may be formed in accordance with semiconductor-on-insulator (SOI) technology, wherein the source, channel and drain regions of the transistors are formed in a relatively thin semiconductor layer that is separated from a support substrate, which may be a semiconductor substrate, for example a silicon wafer or die, by an electrically insulating layer, which may be a silicon dioxide layer. SOI technology may have some advantages associated therewith, which include a reduced power consumption of a semiconductor-on-insulator circuit compared to a bulk semiconductor integrated circuit having the same performance.
For providing electrical connections to the source regions, drain regions and gate electrodes of field effect transistors, contacts extending through an interlayer dielectric that is provided over the field effect transistors may be formed. The contacts may be formed by etching contact holes through the interlayer dielectric and filling the contact holes with an electrically conductive material such as, for example, tungsten.
For providing electrical insulation between adjacent circuit elements, such as field effect transistors, trench isolation structures that include trenches filled with an electrically insulating material such as, for example, silicon dioxide may be formed. If the active region of a field effect transistor wherein the source, drain and channel regions of the field effect transistor are provided is too short, or if there is a misalignment between the contact holes and the source regions, drains regions and/or gate electrodes in the formation of the contact holes, an etching of the electrically insulating material in the trench isolation structures may occur, so that a contact hole extending through the trench isolation structure and/or the electrically insulating layer of a semiconductor-on-insulator structure is formed. When such a contact hole is filled with the electrically conductive material, it may provide an electric short to the semiconductor material of the support substrate of the semiconductor-on-insulator structure, which may adversely affect the functionality of the integrated circuit.
Furthermore, gate structures of field effect transistors may have an overlap with a trench isolation structure adjacent the field effect transistors. Thus, there may be portions of the gate structures overlapping the trench isolation structure, wherein the gate insulation layers of the gate structures are provided on the electrically insulating material in the trench isolation structure.
In some techniques for the manufacturing of integrated circuits, cleaning processes may be performed wherein a cleaning agent is used that can attack the electrically insulating material in the trench isolation structures, which can occur, in particular, in embodiments wherein the electrically insulating material in the trench isolation structures includes silicon dioxide. In such cleaning processes, an under etching of the portions of the gate structures that overlap the trench isolation structure may occur, wherein the electrically insulating material of the trench isolation structure is removed below the gate insulation layers of the gate structures. Thus, the cleaning agent can contact the high-k material of the gate insulation layers. Thus, an etching of the high-k material by the cleaning agent may occur, so that portions of the gate insulation layers are removed. In some situations, even portions of the gate insulation layers over the active regions of the field effect transistors may be etched by the cleaning agent, which can adversely affect the functionality of the integrated circuit, effectively killing the device.
The present disclosure provides semiconductor structures and methods for the formation thereof which may help to substantially overcome or at least reduce the above-mentioned issues.